Reference Implementations for Intel® Architecture Approximation Instructions...
Author: Marius Cornea, Intel CorporationWe are providing two files, RECIP14.c and RECIP28EXP2.c, containing reference implementations for the scalar versions of 10 approximation instructions introduced...
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Putting Your Data and Code in Order: Optimization and Memory – Part 1
This series of two articles discusses how data and memory layout affect performance and suggests specific steps to improve software performance. The basic steps shown in these two articles can yield...
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Putting Your Data and Code in Order: Data and layout - Part 2
In this pair of articles on performance and memory covers basic concepts to provide guidance to developers seeking to improve software performance. These articles specifically address memory and data...
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Intel® Advisor XE 2016 Update 3 What’s new
We’re pleased to announce new version of the Vectorization Assistant tool - Intel® Advisor XE 2016 Update 3. Below are highlights of the new functionality and improvements. Support for Intel® Xeon Phi™...
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Performance Gains for Ayasdi Analytics* on the Intel® Xeon® Processor E7-8890 V3
IntroductionAyasdi deploys vertical applications that utilize Topological Data Analysis to extract value from large and complex data. The Ayasdi platform incorporates statistical, geometric, and...
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Understanding NUMA for 3-Dimensional Finite Difference (3DFD) Code with an...
This article demonstrates techniques that software developers can use to identify and fix NUMA-related performance issues in their applications using the latest Intel® software development tools.Quick...
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Whatever the Weather: The Intel Five Step Framework for Code Modernization
Weather forecasting is a crucial aspect of modern life, enabling efficient planning and logistics, while also protecting life and property through timely warnings of severe conditions. But accurate,...
View ArticleIntel® IPP Functions Optimized for Intel® Advanced Vector Extensions 2...
Here is a list of Intel® Integrated Performance Primitives (Intel® IPP) functions that are optimized for Intel® Advanced Vector Extensions 2 (AVX2) on Haswell and Intel® microarchitecture code name...
View ArticleIntel® C++ Compiler 17.0 Release Notes
This page provides links to the current Release Notes for the Intel® C++ Compiler 17.0 component of Intel® Parallel Studio XE 2017 for Windows*, Linux* and OS X*. To get product updates, log in to the...
View ArticleIntel® IPP Functions Optimized for Intel® Advanced Vector Extensions 512...
Below is the list of Intel® Integrated Performance Primitives (Intel® IPP) functions that are optimized for Intel® Advanced Vector Extensions 512 (Intel® AVX-512). Among these functions, 135 functions...
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Accelerating SSL Load Balancers with Intel® Xeon® E5 v4 Processors
Examining the impact of the ADCX, ADOX, and MULX instructions on haproxy performanceOne of the key components of a large datacenter or cloud deployment is the load balancer. When it’s a service...
View ArticleReference Implementations for Intel® Architecture Approximation Instructions...
Author: Marius Cornea, Intel CorporationWe are providing two files, RECIP14.c and RECIP28EXP2.c, containing reference implementations for the scalar versions of 10 approximation instructions introduced...
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Webcast: Parallel computing on Intel® Architecture
Regulatory pressures, which increase the amount of required computing, the need to improve operational efficiency and competition, which require faster computing, are among the drivers that incent...
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Accelerating SSL Load Balancers with Intel® Xeon® E5 v4 Processors
Examining the impact of the ADCX, ADOX, and MULX instructions on haproxy performanceOne of the key components of a large datacenter or cloud deployment is the load balancer. When it’s a service...
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Fast Computation of Huffman Codes
AbstractThe generation of Huffman codes is used in many applications, among them the DEFLATE compression algorithm. The classical way to compute these codes uses a heap data structure. This approach is...
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Recognizing and Measuring Vectorization Performance
Vectorization promises to deliver as much as 16 times faster performance by operating on more data with each instruction issued. The code modernization effort aims to get all software running faster by...
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Migrating Applications from Knights Corner to Knights Landing Self-Boot...
While there are many different programming models for the Intel® Xeon Phi™ coprocessor (code-named Knights Corner (KNC)), this paper lists the more prevalent KNC programming models and further...
View ArticleIntel® IPP Functions Optimized for Intel® Advanced Vector Extensions 2...
Here is a list of Intel® Integrated Performance Primitives (Intel® IPP) functions that are optimized for Intel® Advanced Vector Extensions 2 (AVX2) on Haswell and Intel® microarchitecture code name...
View ArticleHow to detect Knights Landing AVX-512 support (Intel® Xeon Phi™ processor)
The Intel® Xeon Phi™ processor, code named Knights Landing, is part of the second generation of Intel Xeon Phi products. Knights Landing supports Intel® AVX-512 instructions, specifically AVX-512F...
View ArticleCompiling for the Intel® Xeon Phi™ processor and the Intel® AVX-512 ISA
IntroductionThis document briefly gives an overview of the Intel® Advanced Vector Extensions 512 (Intel® AVX-512) and shows different ways to build an application for the Intel® Xeon Phi™ processor...
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